desktop ddr3 4gb ddr3 4gb

used in capturing data at the receiver
8) Data inputs and outputs are synchronzed with DQS.
9) DQS is edge aligned with data for read, center aligned with data for write.
10) Differential clock inputs (CK and CK).
11) DLL aligns DQ and DQS transitions with CK transitions
12) Commands entered on each positive CK edge: Data and data mask referenced to both edges of DQS.
13) Four internal banks for concurrent operation (component).
14) Data mask(DM) for write data.
15) Auto precharge option for each burst access
16) Programmable burst length: 2, 4, 8
17) Programmable/CAS latency (CL): 3
18) Programmable output driver strength: Normal/weak
19) Refresh cycles: (8192 refresh cycles/64ms) .
20) 7.8US maximum average periodic refresh interval.
21) Posted CAS by programmable additive latency for better command and data bus efficiency
22) Off-chip-driver impedance adjustment and on-die-termination for better signal quality .
23) DQS can be disabled for single-ended data strobe operation
24) 2 variations of refresh
25) Auto refresh
26) Self refresh.


	< Back

	JOINWIN INDUSTRIAL DEVELOPMENT LTD

	About this company : Shenzhen JOINWIN Technology Co., Ltd. founed in 2004, inegrates R&D, sale and production. We are a professional manufacturer of PC and laptop memory module, mobile phone ,UMPC mini laptop, DVD a nd CD writer, USB flash drive, memory card, MP3/MP4/MP5 player, and other electronic products

	Contact : Ellen Dong, sales
	Headquarters : 20C, North Block, Guangye Bldg, Fum, Shenzhen, guangdong, 518000, China
	Phone : 86 13632714087, Fax : 86 755 83952193
	Website : Log on to trade instantly , Email : Log on to trade instantly

			desktop ddr3 4gb ddr3 4gb 1) DDR 400/333 & DDRII 533/667/800 & DDR3/1066/1333/1600�MHz. 2) 168/184/240-pin socket type dual in line memory module (DIMM) . 3) 2.6V power supply 4) Data rate: 400/333/533/667/800M1066/1333MHZ/1600mhz (max). 5) 2.5 V (SSTL-2 compatible) I/O for DDR I products, 1.8Vpower supply for DDR II products 6) Double-data-rate architecture, two data transfers per clock cycle. 7) Bi-directional, differential data strobe (DQS) is transmitted/received with data, to be used in capturing data at the receiver 8) Data inputs and outputs are synchronzed with DQS. 9) DQS is edge aligned with data for read, center aligned with data for write. 10) Differential clock inputs (CK and CK). 11) DLL aligns DQ and DQS transitions with CK transitions 12) Commands entered on each positive CK edge: Data and data mask referenced to both edges of DQS. 13) Four internal banks for concurrent operation (component). 14) Data mask(DM) for write data. 15) Auto precharge option for each burst access 16) Programmable burst length: 2, 4, 8 17) Programmable/CAS latency (CL): 3 18) Programmable output driver strength: Normal/weak 19) Refresh cycles: (8192 refresh cycles/64ms) . 20) 7.8US maximum average periodic refresh interval. 21) Posted CAS by programmable additive latency for better command and data bus efficiency 22) Off-chip-driver impedance adjustment and on-die-termination for better signal quality . 23) DQS can be disabled for single-ended data strobe operation 24) 2 variations of refresh 25) Auto refresh 26) Self refresh.
	> Add to cart

About Us \| Register \| Login \| Join \| Trade \| Forum \| Cart \| \| \| Know-How \| Trading Precaution \| Phishing Alerts \| SOA^OnDemand! \| VAR 360 \| RSS Feed
	Copyright © 2024 MarginUp All Rights Reserved. MarginUp User Agreement and Privacy Policy.